1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a page mode reading controlling/sense amplifier controller in a semiconductor memory device having a page access mode such as SRAM (static random access memory) and ROM (read only memory).
2. Description of the Related Art
There has been used a semiconductor memory device having a page access mode in which a specific address can be accessed at a high speed. In a reading operation of the page access mode, a page mode column address is changed in a state that a plurality of data of a memory cell array is read up to a sense amplifier in parallel. Thereby, data of the plurality of columns is switched at a high speed to be outputted. Therefore, in the page access mode, though there is a limitation in the point of the random access, a high-speed reading operation can be realized, and this is very useful in the case of reading data in series.
FIG. 1 is a block diagram showing a conventional reading circuit, which is a part of an SRAM having a page access mode.
The SRAM has, for example, a four-bit page access mode. In FIG. 1, reference numeral 10 is a memory cell, 11: a memory cell array, 12: a row decoder for selecting a memory cell to read data of a plurality of memory cells from the memory cell array 11 in accordance with row address A2 to An, 13: a sense amplifier for sensing data read to a pair of I/O,/(I/Oi) lines through a pair of bit lines BLi,/BLi and each column selection circuit 14 from selected plurality of memory cells, 16: a page selection circuit for selecting data outputted from said sense amplifier 13 to a pair of data lines DLi,/DLi, 17: a page decoder for selecting the page selection circuit 16 in accordance with page mode address A0 and A1, and 18: an output buffer for outputting data, which is outputted to a pair of data bus lines BUS,/BUS from the page selection circuit 16, to an output terminal 19.
The following will explain a reading operation of the SRAM of FIG. 1.
In the reading operation in a normal access mode, address signals A0 to An are set, 4-bit data selected by row addresses (normal addresses) A2 to An is read up to the sense amplifier 13 in parallel, and one-bit data is selected in accordance with address signals A0 and A1, and outputted.
In the reading operation in the page access mode, address signals A0 to An are set. On reception of transition of the address signal, 4-bit data (page data) is selected in accordance with row addresses A2 to An, and read up to the sense amplifier 13 in parallel. Then, one-bit data is selected in accordance with the page mode addresses A0 and A1, and outputted.
Then, the page mode address signals A0 and A1 are transited, and the residual 3-bit data is sequentially selected, and sequentially outputted to the output terminal 19 through the output buffer 18, thereby making it possible to perform a high-speed reading.
Moreover, for continuously reading page data, the contents of the row addresses A2 to An is changed, new 4-bit data is selected, and read up to the sense amplifier 13 in parallel. Then, one-bit data is selected in accordance with the page mode addresses A0 and A1, and outputted. Then, the page mode address signals A0 and A1 are transited, and the residual 3-bit data is sequentially selected, and sequentially outputted to the output terminal 19 through the output buffer 18.
In the conventional SRAM reading circuit having a page access mode, since it is needed that the sense amplifier 13 be always activated thereby setting read data in an output state in the page access mode, consumption current of the sense amplifier 13 is high.